/**
  ******************************************************************************
  * @file    fsmc_transfer.c
  * @author  yan
  * @version V1.0
  * @date    2016-11-26
  * @brief   This file provides the data transfer function based on the FSMC
  ******************************************************************************
	*/
	
	
/* Includes ------------------------------------------------------------------*/
#include "fsmc_transfer.h"

/** @defgroup FSMC_TRANSFER 
  * @brief Parallel data transfer modules
  * @{
  */ 

/** @defgroup FSMC_Private_Defines
  * @{
  */
	
	
#define Bank1_SRAM4_ADDR    ((uint32_t)0x6c000000)   

/**
  * @}
  */
	
	
/** @defgroup GPIO_Private_Functions
  * @{
  */
	
	
/**
  * @brief  Initialize the FSMC parallel port data transfer module
  * @param  None
  * @retval None
  */
	
void _m_fsmctransfer_init(void)
{
	
  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;  
  FSMC_NORSRAMTimingInitTypeDef  p;  
  GPIO_InitTypeDef GPIO_InitStructure;   
    
  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |  
                         RCC_APB2Periph_GPIOF, ENABLE);  
  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);

/*-- GPIO Configuration ------------------------------------------------------*/  
  /*!< SRAM Data lines configuration */  
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |  
                                GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;  
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;  
  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;  
  GPIO_Init(GPIOD, &GPIO_InitStructure);   
    
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |  
                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |   
                                GPIO_Pin_15;  
  GPIO_Init(GPIOE, &GPIO_InitStructure);  
    
  /*!< SRAM Address lines configuration */  
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |   
                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |   
                                GPIO_Pin_14 | GPIO_Pin_15;  
  GPIO_Init(GPIOF, &GPIO_InitStructure);  
    
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |   
                                GPIO_Pin_4 | GPIO_Pin_5;  
  GPIO_Init(GPIOG, &GPIO_InitStructure);  
    
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;   
  GPIO_Init(GPIOD, &GPIO_InitStructure);  
     
  /*!< NOE and NWE configuration */    
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;  
  GPIO_Init(GPIOD, &GPIO_InitStructure);  
    
  /*!< NE4 configuration */  
	
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;   
  GPIO_Init(GPIOG, &GPIO_InitStructure);  
    

/*-- FSMC Configuration -----------------------------------------------------*/  
  p.FSMC_AddressSetupTime = 0x08;  
  p.FSMC_AddressHoldTime = 0x00;  
  p.FSMC_DataSetupTime = 9;  
  p.FSMC_BusTurnAroundDuration = 0x00;  
  p.FSMC_CLKDivision = 0x00;  
  p.FSMC_DataLatency = 0x00;  
  p.FSMC_AccessMode = FSMC_AccessMode_A;  
	
  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;  
  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;  
  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;  
  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;  
  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;  
  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;    
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;  
  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;  
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;  
  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;  
  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;  
  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable;  //
  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;  
  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;  
  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;  
	
  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);   
  /*!< Enable FSMC Bank1_SRAM Bank */  
  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);    
}
	
/**
  * @brief  Parallel port data write function
	* @param  pBuffer		:write data
	*	@param	WriteAddr	:write address 
  * @retval None
  */
void _m_fsmctransfer_Write(uint16_t pBuffer, FSMC_TRANSFER_Address WriteAddr)  
{  
    uint16_t i,j;
    for(j = 20;j > 0 ; j--)
      for(i = 3000;i > 0 ; i--);
    *(uint32_t *) (Bank1_SRAM4_ADDR + WriteAddr) = pBuffer<<16|pBuffer; 
    
}  


/**
  * @brief  Parallel port data write function
	* @param  ReadAddr	:read address
  * @retval out of data value 
  */
uint16_t _m_fsmctransfer_Read(FSMC_TRANSFER_Address ReadAddr)  
{  
    uint16_t i,j;
    for(j = 10;j > 0 ; j--)
      for(i = 3000;i > 0 ; i--);
    uint16_t pBuffer;   
    pBuffer = *(__IO uint32_t*) (Bank1_SRAM4_ADDR + ReadAddr);     
    return pBuffer;   
}  


/**
  * @}
  */
	


/** @defgroup FSMCTRANSFER_Exported_Structure
  * @{
  */

struct _m_fsmctransfer_dev fsmctransfer_dev=
{
	.init 	=	_m_fsmctransfer_init,
	.write	=	_m_fsmctransfer_Write,
	.read 	= _m_fsmctransfer_Read
	
};


/**
  * @}
  */
	
	
/**
  * @}
  */

